1. Field of the Invention
The present invention relates generally to digital-to-analog converter (DAC) circuits, and more particularly to DAC circuits for improved current switch linearity.
2. Background
Recent advances in semiconductor manufacturing technology and computer architecture have combined to provide relatively low-cost computer platforms having sufficient computational power to enable visual computing. In addition to being computationally robust, a visual computing platform must also have a high performance graphics subsystem, which typically includes a DAC.
DACs of the type commonly used for driving video and graphics display devices are called current mode DACs. Current mode DACs are made up of many current sources (e.g., 255 in an 8-bit linearly weighted DAC), each current source representing one or more least significant bits (LSB) of the DAC output. The currents are steered to either the output or to another node, typically ground, depending on the digital input code presented to the DAC for conversion. As shown in FIG. 1, the currents are summed and then converted to an output voltage by a resistor (RLOAD) connected from the output pad to ground. An important aspect of a DAC is the linearity achieved in the DAC output as the input codes to the DAC are changed.
Many DACs are implemented using Complementary Metal Oxide Semiconductor (CMOS) processes. CMOS processes make both n-channel field effect transistors (NFETs) and p-channel field effect transistors (PFETs) available to circuit designers. As is well known, FETs have various operating regions, for example unsaturated and saturated, wherein the current that flows between the source and drain of a FET may be either strongly related to the drain-to-source voltage, or weakly related to (or even independent on the drain-to-source voltage. In designing circuits having linear characteristics, it is less difficult to achieve the desired signal processing goal by operating FETs in the saturated region of operation where the current flowing between the source and drain is substantially a function of the applied gate-to-source voltage (Vgs).
As the physical dimensions of transistors continue to shrink with more advanced semiconductor manufacturing techniques, circuit designers have been constrained to circuits that require lower and lower operating voltages.
The reduction of operating voltages makes it increasingly difficult to maintain the current switches in a DAC in the saturated region of operation.
What is needed is a method and apparatus for providing improved linearity to CMOS DAC circuits operated at supply voltages that are low compared to the drain-to-source voltages required for FETs to operate in the saturated region.
Briefly, a DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals.
In one embodiment of the present invention, a pair of inverting logic gates, coupled between a power rail and a node positively offset from ground, are used to drive the current switches in a DAC stage.
Various other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.